1. Field of the Disclosure
The present invention relates to multilayer electronic support structures which are generally thin yet rigid and stiff, and to methods of fabrication thereof.
2. Description of the Related Art
Advanced IC substrates in the formats of Flip Chip Ball Grid Arrays (FCBGA) and Flip Chip Scale Packages (FCCSP) usually employ a ‘core’ structure that is typically a Glass/Polymer dielectric composite that has a small number, typically 2 or more copper layers on one or both sides. The copper layers are electrically interconnected using Plated through holes (PTHs).
The Glass/Polymer dielectric composite core serves as a base on which a multilayer stack is built up. The multilayer stack consists of layers of dielectric, typically polymer film or prepreg, that sequentially alternate with layers of copper metal that are interconnected by filled copper micro vias.
The finished FCBGA or FCCSP substrates units are required to demonstrate a high degree of flatness and are required to be warp free in order to support subsequent process steps, such as the attaching of active (IC) and passive components in what is sometimes known as “first level assembly”.
To balance stresses during processing, which could result in warpage or delamination, the multilayer stack is preferably built up on both sides of the base. After the first level assembly, the total unit, including the IC(s), passive components and the substrate that carries them, is sometimes known as an ‘IC Package’.
The IC Package requires attachment to the next level of the electronic subsystem, which usually includes a Printed Circuit Board (PCB). The series of processes that are used to attach the IC Package to the PCB are sometimes referred to as ‘second level assembly’.
Many modern electronic systems, particularly handheld devices such as smart phones, tablets and the like, require additional functionality, enhanced electrical performance, lower heat dissipation and ever slimmer IC packages. Consequently, the first and second level assembly processes become ever more complex since the IC substrate may carry on it 3D package architecture, such as a series of stacked dies or even another IC package using what is sometimes referred to as ‘PoP’, an acronym for Package on Package.
It will be appreciated from the above discussion, that advanced IC substrates in FCBGA or FCCSP formats are required to have superior flatness, not only during their own fabrication, but also in subsequent processing, since they are typically exposed to elevated temperatures and harsh processing conditions during both first and second level assembly processing.
In consequence of the above, warping of the IC substrate may severely reduce yields during first and second level assembly, especially when die stacking and 3D PoP architectures are employed. Warped FCBGA and FCCSP substrates or IC packages may cause cracks in the Flip Chip bumps interconnecting the IC to the substrate, cracks in the BGA balls that interconnect the IC package to the PCB (or to another IC package in PoP configuration) or even die cracking, all of which may lead to system failures.
The demand for ever thinner IC substrates is increasing, driven by the need to meet low form factor space requirements for modern handheld devices and to achieve lower inductance and lower thermal impedance with yet higher contact points for more device functionality. Consequently, the microelectronics industry has been considering employing what has been referred to as ‘Coreless’ IC substrates that have FCBGA or FCCSP type formats and are constructed out of a build up of layers, but do not include the central ‘core’ section. Coreless substrates of this type have significantly reduced thickness, improved system inductance due to the short via paths to and from the IC, and improved thermal impedance. However, coreless substrates are also more susceptible to warping due to their inherent lack of mechanical stiffness and the lack of support that would normally be provided by the absent core section. These problems may become acute during exposure to elevated processing temperatures when fabricating the first and second level assemblies thereupon, and particularly in consequence of the thermal processes that are employed to stack dies and/or packages.
Various coreless substrate technologies that feature build up structures with dielectric films have been proposed in recent years. Most coreless substrate technologies require an external metal frame stiffener mounted on the IC side of the substrate in order to maintain an acceptable level of flatness and to compensate for the lack of core in the structure. It will, however, be appreciated that such external stiffeners occupy premium real estate space on the top surface of the substrate, and this occupied space is unavailable for other purposes, such as for mounting passive components mounting and/or pads that may be required to couple an additional IC package stacked on the substrate surface.
One approach that addresses this problem is the use of coreless IC substrates as developed by AMITEC and as described in U.S. Pat. No. 7,682,972, U.S. Pat. No. 7,669,320 and U.S. Pat. No. 7,635,641 to Hurwitz et al. Amitec's technology allows the fabrication of a coreless substrate that may employ glass fabric/polymer composites materials (prepregs) that enhance the over all substrate flatness and warpage resistance and therefore eliminates the need for an external metal frame stiffener as described above.
Nevertheless, the ever increasing requirement demands to lower the thickness of substrates and to reduce their thermal impedances pose challenges that even the AMITEC coreless structures as described in U.S. Pat. No. 7,682,972, U.S. Pat. No. 7,669,320 and U.S. Pat. No. 7,635,641 may find hard to overcome.